The present invention relates to an error checking apparatus for checking a data error in a digital data processor.
The number of bits of data to be processed in a digital computer as a digital data processor is increasing due to the development of microprocessor techniques. A system for processing data having 64 bits or more in a DMA memory bus has been developed. Error checking codes such as an error correction code and a parity bit are added to the digital data to be processed in such a system, and the data errors are thus checked.
Data error detection and error correction can be performed by the error checking codes to some extent. According to this scheme, however, it is very difficult to detect the data error position or the cause of the data error.